1. Field of the Invention
The present invention relates to a method of inspecting an electronic circuit including an integrated circuit.
2. Description of the Related Art
Most electric and electronic circuits include an integrated circuit therein. Usually, the integrated circuit is packaged in a resinous case with a plurality of conductive pins projecting from the case. The size of the integrated circuit and the intervals between the pins have been made suitable for a quality inspection to be made without difficulty.
However, as demand for increasing the performance of the integrated circuit has become stronger, the size of the integrated circuit and the intervals between the pins have been decreased.
There is, so called, a margin test in the quality inspection. The margin test is to examine the on-off operation of the integrated circuit while a certain electric voltage is applied to one or more of the pins by an inspection probe. As the intervals between the pins become shorter, it is more difficult to bring the inspection probe in contact with the pins.
In order to solve the above problem, JP-A-5-72280 proposes inspection lands formed on a circuit board to make the margin test after the integrated circuit is mounted on the board. However, because such inspection lands necessitate an additional test space in the circuit board besides the mounting space, it does not help to decrease the size of the electronic circuit.